The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices formed by stacking chips by a chip-on-chip technique.
In systems such as digital televisions and recorders, the amount of handled data is dramatically increasing with an increase in the number of functions. This increases the capacity of semiconductor memories mounted in the systems. Not only that, semiconductor memories performing high-rate data transfer have been increasingly demanded. In addition, in order to mount a large number of semiconductor memories in a system, semiconductor devices including a memory controller for integrating semiconductor logic circuits and the memories are being developed.
To integrate a logic circuit and a memory, there are a system-on-chip (SoC) formed by integrating a logic circuit and a memory in a single chip, and a system-in-package (SiP) formed by stacking and storing a logic circuit chip and a memory chip in a single package. Out of them, the SiP is well-balanced to meet the demand for lower costs, higher function, lower power consumption, miniaturization, a lower weight, flexible specifications, etc., which are required for a system. Although it depends on the system configuration and the specification, SiPs are increasingly advantageous in general.
SiPs are divided into four types of a chip-on-chip (CoC) type, a chip-stack type, a package-on-package type, and a substrate connection type based on the structural differences. Out of them, the CoC type SiP is formed by stacking a chip on a semiconductor chip, and connecting the circuit formation surfaces of the chips (see, e.g., Japanese Unexamined Patent Publication No. 2010-141080). These two (i.e., upper and lower) chips include a number of bumps for connection on their circuit surfaces. These bumps are generally much smaller than bumps for flip-chip bonding and called “microbumps.” In CoC type SiPs, a most suitable design or fabrication process of the upper and lower chips can be selected, thereby increasing the flexibility in selecting the system structure.
In CoC type SiPs, in bonding the upper and lower chips with microbumps, the location of chip electrodes are optimized depending on the locations of the CoC connecting portions (i.e., microbumps). Therefore, in general, at least one of the upper and lower chips has a structure of re-distribution from the chip electrodes to the CoC connecting portions.